The prior art is replete with different techniques and processes for fabricating semiconductor devices such as metal oxide semiconductor (MOS) transistors. In accordance with typical fabrication techniques, a MOS transistor is formed by creating a device structure on a semiconductor substrate, where the device structure includes a gate stack formed on a layer of semiconductor material, and source and drain regions formed in the semiconductor material to define a channel region under the gate stack. Some transistor devices are fabricated using a replacement gate technique; in accordance with this technique, temporary gate material (typically polycrystalline silicon) is removed and then replaced with a different gate material (typically a metal). In this regard, FIG. 1 is a cross sectional view of a semiconductor device structure 100 in a state prior to removal of temporary gate material 102. The temporary gate material 102 is located between two sidewall spacers 104.
Ideally, the sidewall spacers 104 retain their shape after the temporary gate material 102 has been removed. The resulting space between the sidewall spacers 104 can then be filled with the replacement gate material. Unfortunately, the sidewall spacers 104 tend to bend or deform inwardly after removal of the temporary gate material 102. FIG. 2 is a cross sectional view of the semiconductor device structure 100 after the temporary gate material 102 has been removed. FIG. 2 depicts (in an exaggerated manner) how the sidewall spacers 104 deflect inwardly toward each other in the absence of the temporary gate material 102. It becomes difficult or impossible to fill the space 106 with the replacement gate material when the sidewall spacers 104 are deflected in this manner, because the deflected sidewall spacers 104 cause the deposited material to form overhangs near the upper opening, and the overhanging material can “seal” the opening before the space 106 is completely filled. This problem is exacerbated when small manufacturing node technologies (e.g., 32 nm and beyond) are employed to fabricate the semiconductor devices.
Accordingly, it is desirable to have a semiconductor device fabrication process that addresses the limitations and shortcomings of conventional replacement gate processes. In particular, it is desirable to have a semiconductor device fabrication process that improves the effectiveness of the gate material filling step.